The present invention relates to power consumption of integrated circuit designs such as circuits used in medical devices, particularly implantable devices. More particularly, the present invention pertains to providing adjustable clock control and/or multiple supply voltage levels for operation of such circuits.
Various devices require operation with low power consumption. For example, hand-held communication devices require such low power consumption and, in particular, implantable medical devices require low power capabilities. With respect to implantable medical devices, for example, microprocessor-based implantable cardiac devices, such as implantable pacemakers and defibrillators, are required to operate with a lower power consumption to increase battery life and device longevity.
Generally, such low power devices are designed using complementary metal oxide semiconductor (CMOS) technology. CMOS technology is generally used because such technology has the characteristic of substantially zero xe2x80x9cstaticxe2x80x9d power consumption.
Power consumption of CMOS circuits consists generally of two power consumption factors, namely xe2x80x9cdynamicxe2x80x9d power consumption and static power consumption. Static power consumption is only due to current leakage as the quiescent current of such circuits is zero. Dynamic power consumption is the dominant factor of power consumption for CMOS technology. Dynamic power consumption is basically due to the current required to charge internal and load capacitances during switching, i.e., the charging and discharging of such capacitances. Dynamic power (P) is equal to: xc2xdCVDD2F, where C is nodal capacitance, F is the clock or switching frequency, and VDD is the supply voltage for the CMOS circuit. As can be seen from the formula for calculating dynamic power (P), such dynamic power consumption of CMOS circuits is proportional to the square of the supply voltage (VDD). In addition, dynamic power (P) is proportional to the switching or clock frequency (F).
In accordance with the formula for dynamic power consumption, it has been effective conventionally in CMOS integrated circuit designs to scale down the supply voltage for an entire device (e.g., hybrid) or integrated circuit (IC), i.e., operate the circuit at low supply voltages, to reduce power consumption for such designs. For example, in the MEDTRONIC SPECTRAX(copyright) product of circa 1979, IC circuitry was powered by one lithium iodine (as opposed to the two cells employed in the prior art). This reduced the supply voltage to 2.8 volts from 5.6 volts, thus reducing overhead current. Voltages required to be greater than 2.8 volts were generated by a voltage doubler, or alternatively by a charge pump (e.g., output pacing pulses). In the MEDTRONIC SYMBOLS(copyright) product of circa 1983, for example, logic circuitry was powered by a voltage regulator controlling the IC supply voltage to a xe2x80x9csum of thresholdsxe2x80x9d supply. This regulator provided a supply to the IC (i.e., VDD) of several hundred millivolts above the sum of the n-channel and p-channel thresholds of the CMOS transistors making up the IC. This regulator was self calibrating regarding manufacturing variations of the transistor thresholds.
Other devices reduced power consumption in other manners. For example, various device designs have shut-down analog blocks and/or shut-off clocks to logic blocks not being used at particular times, thereby reducing power. Microprocessor based devices have historically used a xe2x80x9cburst clockxe2x80x9d design to operate a microprocessor at a very high clock rate (e.g., generally 500-1000 Kilohertz (KHz)), for relatively short periods of time to gain the benefit of a xe2x80x9cduty cyclexe2x80x9d to reduce average current drain. A much lower frequency clock (e.g., generally 32 KHz) is used for other circuitry and/or the processor when not in the high clock rate mode, i.e., burst clock mode. Many known processor based implanted devices utilize the burst clock technique. For example, implanted devices available from Medtronic, Vitatron, Biotronixc3xa7, ELA, Intermedics, Pacesetters, InControl, Cordis, CPI, etc., utilize burst clock techniques. A few illustrative examples which describe the use of a burst clock are provided in U.S. Pat. No. 4,561,442 to Vollmann et al., entitled xe2x80x9cImplantable Cardiac Pacer With Discontinuous Microprocessor Programmable Anti Tachycardia Mechanisms and Patient Data Telemetry,xe2x80x9d issued Dec. 31, 1985; U.S. Pat. No. 5,022,395 to Russie, entitled xe2x80x9cImplantable Cardiac Device With Dual Clock Control of Microprocessor,xe2x80x9d issued Jun. 11, 1991; U.S. Pat. No. 5,388,578 to Yomtov et al., entitled xe2x80x9cImproved Electrode System For Use With An Implantable Cardiac Patient Monitor,xe2x80x9d issued Feb. 14, 1995; and U.S. Pat. No. 5,154,170 to Bennett et al., entitled xe2x80x9cOptimization for Rate Responsive Cardiac Pacemaker,xe2x80x9d issued Oct. 13, 1992.
FIG. 1 illustrates graphically energy/delay versus supply voltage for CMOS circuits such as CMOS inverter 10 shown in FIG. 2 for illustrative purposes. Inverter 10 is provided with a supply voltage, VDD, which is connected to the source of a PMOS field effect transistor (FET) 12. PMOS FET 12 has its drain connected to the drain of a NMOS FET 14 whose source is connected to ground. In this configuration, an input Vi applied to both the gates of FETs 12, 14 is inverted to provide output Vo. Simply stated, one clock cycle, or logic level change, is used to invert the input Vi to Vo.
As shown in FIG. 1, the circuit logic delay increases drastically as the supply voltage is reduced to near one volt, as represented by delay line 16 and energy/delay line 18. As such, reducing of the supply voltage (VDD) continuously to lower levels is impractical because of the need for higher supply voltages when higher frequency operation is required. For example, generally CMOS logic circuits must periodically provide functionality at a higher frequency, e.g., burst clock frequency. However, as the supply voltage (VDD) is decreased, such energy consumption is reduced by the square of the supply voltage (VDD) as is shown by energy consumption line 20. Therefore, speed requires a higher supply voltage (VDD) which is in direct conflict with low power consumption.
Other problems are also evident when lower supply voltages (VDD) are used for CMOS circuit designs. When a lower supply voltage is selected, static leakage current losses may arise, particularly at lower frequencies, due to increased static leakage current losses.
Various techniques for reducing power consumption in devices are known in the art, some examples of which may be found in the references listed in Table 1 below.
All references listed in Table 1 herein above are hereby incorporated by reference in their respective entireties. As those of ordinary skill in the art will appreciate readily upon reading the Summary of the Invention, Detailed Description of the Embodiments, and claims set forth below, at least some of the devices and methods disclosed in the present application, including those disclosed in the reference listed in Table 1 hereinabove, may be modified advantageously in accordance with the teachings of the present invention.
The present invention has certain objects. That is, various embodiments of the present invention provides solutions to one or more problems existing in the prior art respecting circuitry design having lower power consumption, particularly with respect to implantable medical devices. Those problems include: CMOS, CML, SOS, SOI, BICMOS, PMOS and/or NMOS circuits having too large of a dynamic power consumption which reduces battery life; the inability to utilize low voltage supply levels effectively; lack of ability to provide adequate processing capabilities such as high processing capabilities including telemetry uplink/downlink, morphology detection, initialization of devices, while still providing low processing capabilities such as sensing intrinsic beats, pacing, low speed telemetry, with the desired power consumption; and the inability to provide circuit designs that operate at lower frequencies and thus lower power consumption as opposed to the use of higher speed clocks such as burst clocks.
In comparison to known techniques for reducing power consumption in circuit designs, various embodiments of the present invention may provide one or more of the following advantages: reduced power consumption through the use of a lower voltage supply (VDD); reduced power consumption by decreased clock frequency for circuit designs; increased longevity of circuits, particularly implantable device circuitry; provide a potential reduction in product size; minimize static leakage current losses, i.e., static power consumption; provide multi-processor designs, DSP designs, and high performance processing designs with additional features/function opportunities due to the ability to reduce power with respect to other xe2x80x9crequiredxe2x80x9d features and functions; and provide for substantial reduction in current drain.
Some embodiments of the invention include one or more of the following features: operation of circuits to complete a desired function (generally completed in a predetermined number of clock cycles) at a clock speed of a lower or intermediate level to adequately complete processing just-in-time prior to the next required functional process; using substantially an entire predetermined time period (e.g., one based on physiological events such as during a blanking interval, upper rate interval, escape interval, refractory interval, and pulse generator/programmer handshake, etc.) to perform a function at a clock speed such that the function is completed just prior to any next required functional process; providing one or more voltage sources or a voltage source operable to provide one or more supply voltages tailored for various circuit functions of a single integrated circuit; operatively connecting a clock source to two or more circuits such that different circuits are operated at different clock frequencies; adjusting supply voltage levels connected to one or more circuits based on the clock frequencies used for controlling operation of the circuits; adjusting back gate bias of a circuit based on the supply voltage level applied to the circuit; providing different supply voltage levels to processing circuitry depending upon the function being performed by the processing circuitry; operating processing circuitry at different clock frequencies depending upon the function being performed by the processing circuitry; changing the supply voltage level xe2x80x9con the flyxe2x80x9d as required by specific circuit timing functions required for various circuit or processing circuitry functionality based on clock frequencies used to control operation of such circuitry; employing various ones or combinations of the foregoing features in CMOS, CML (Current Mode Logic), SOS (Silicon on Sapphire), SOI (Silicon on Insulator), BICMOS, PMOS and/or NMOS circuitry.